1. Field of the Invention
The invention generally relates to the field of high-speed, low latency electronic processors utilizing reconfigurable logic devices such as field programmable gate arrays or “FPGAs”.
More specifically, the invention relates to a high-speed electronic processor core comprising direct processor-to-memory interconnectivity that avoids the latency and bus contention delays of prior art processors incorporating bused memory in connection with an FPGA.
2. Description of the Prior Art
The ability to perform massively parallel data processing operations at high data/line rates in applications such as intrusion detection, detection of malicious code or viruses, analysis of DOS attacks or statistical inspection of IPV4 and IPV6 internet packets requires very dense, efficient, low-latency, processor-to-memory interconnectivity that is lacking in prior art electronic processor devices.
Prior art “bused” processor-to-memory structures and architectures in existing processors lack sufficient density of memory and necessary speed of processor-to-memory interconnectivity that is required for the execution of internet attack detection algorithms, internet traffic deep packet inspection algorithms, packet feature extraction and similar algorithm execution at very high line rates (e.g., 100 Gb/s). Further, prior art “bused memory” architectures lack the ability to scale or to meet overall data processing speeds needed to achieve acceptable results at line rates.
All manner of processing devices such as digital signal processors, microprocessors, microcontrollers, digital network processors, CPLDs or field programmable gate arrays (“processors” herein) are used in applications where low latency, fast access to electronic memory is needed. Field programmable gate array devices or “FPGAs” in particular are well-suited for use in, for instance, the above cyber-security processing applications, due in part to their firmware modifiable nature, i.e., an FPGA can be reconfigured or the code or algorithm it is executing can be modified or replaced in real time at low cost, which benefits are not available in, for instance, in processors using application specific integrated circuits (“ASICs”).
Notwithstanding the great utility of FPGAs, there exist several limitations to the usefulness of these devices in their commercial off the shelf (“COTS”) form. One constraint with respect to prior art FPGA-based architectures is due to the limited amount of memory available within commercially available FPGAs.
A further limitation of prior art FPGA-based processors is illustrated in FIG. 1 in that FPGAs are typically fabricated based on a design rule that assumes a fixed and limited word width, which design is particularly limiting when the FPGA is used in combination with a large amount of off-device memory such as is required in high performance applications such as data processing or networking.
Yet further, when an FPGA is used to read from and write into a memory array that is arranged in a typical planar (i.e., printed circuit board) fashion, a considerable amount of space on the printed circuit board is required in order to physically provide for the combination of the FPGA and the memory. Even when space is available for a large planar area to support the FPGA and surrounding memory, relatively long interconnects and buses between the devices inherently increases parasitic impedance problems and timing delays at high processing speeds with associated degradation in system performance.
What is needed is a processor architecture that takes advantage of the flexibility of FPGA devices, that has a variably wide word width necessary for the diverse algorithms associated with deep packet inspection or cyber-security applications and which has high-speed access to large amounts of electronic memory but that does not have the delay and timing issues associated with memory bus contention and arbitration.
The invention overcomes the deficiencies in the prior art and comprises one or more memory structures such as SRAM, DRAM, SDRAM, or Quad Data Rate SRAM (“QDR”) electronic memory and electrically couples the memories directly to a plurality of FPGAs using an access lead network to provide the FPGA-based processing elements with bus-less access to the one or more memory structures. This configuration provides a high-speed processor core capable of performing massively parallel data processing operations with dramatically reduced memory access delays associated with prior art bus contention or arbitration.